Overview of status registers
The following figure shows the hierarchy of status registers.
Introduction of the registers:
STB, SRE: The status byte (STB) register is at the highest level of the status reporting system. The mask register service request enable (SRE) is associated with the STB as its ENABle part if the STB is structured according to SCPI.
The STB provides a rough overview of the instrument status, collecting the information of the lower-level registers. See also "STB and SRE".
The STB receives its information from:
ESB: The summary bit of standard event status register indicates any enabled bit in the standard event status register (ESR). The standard event status enable (ESE) register is used as the ENABle part of the ESR. Refer to "ESR and ESE".
Output buffer: Contains the messages that the instrument returns to the controller. It is not part of the status reporting system but determines the value of the MAV bit in the STB.
Error/event queue: Refer to "Error queue".
Standard operation event status and questionable event status registers (STATus:QUEStionable, STATus:OPERation): defined by SCPI and contain detailed information on the instrument.
IST, PPE: The individual status (IST) flag combines the entire instrument status in a single bit. The parallel poll enable (PPE) register is associated to the IST flag. Refer to "IST flag and PPE".